1. Field of the Invention
The present invention relates to a receiver and particularly to a CMOS complementary self-biased differential amplifier used in a receiver with IO supply voltage higher than its core MOSFET operating voltage.
2. Description of the Related Art
Various input buffer amplifiers for buffering an input signal prior to coupling that signal to other circuitry are well known in the prior art. Some of these input buffer amplifiers are also known as level shifters, wherein input voltage levels are shifted to be compatible with voltage levels of the associated circuitry. For example, many input voltage levels are specified as being compatible with standard transistor-transistor-logic (TTL) logic levels, that is, a logic threshold of 1.4 volts with a margin of 0.6 volts about the threshold. A typical high logic level TTL signal can be as low as 2.0 volts (VIH parameter), while a low logic level TTL signal can be as high as 0.8 volts (VIL parameter). However, when this TTL level signal is to be used in conjunction with complementary metal oxide semiconductor (CMOS) circuitry, the input levels must be changed to be compatible with the CMOS circuit. Typical CMOS logic thresholds vary from approximately 2.0 to 3.0 volts, while the margin around the threshold can be substantially equal to the difference between the threshold and the supply rails. An input buffer translates the TTL compatible levels of the inputs to the CMOS compatible levels for use with CMOS circuitry inside a CMOS chip. The CMOS chip also includes the input buffer on the chip.
FIG. 3 shows a circuit for a self-biased operational amplifier, used as the input buffer, disclosed in U.S. Pat. No. 6,469,579. The operational amplifier of FIG. 3 may be considered a transconductance amplifier, in that a small-signal current is provided to a load in response to a differential voltage at input nodes 102 and 104. The load in FIG. 3 may be taken as the output resistance of transistor 35B in parallel with the transistor 36B. The operational amplifier of FIG. 3 is self-biasing as no external biasing is needed.
The transistors 31A and 31B are pMOSFETs (p-Metal-Oxide-Semiconductor-Field-Effect-Transistor) arranged as a first differential pair of transistors having their supplies connected to each other, and transistors 32A and 32B are nMOSFETs arranged as a second differential pair having their supplies connected to each other. The two differential pairs are complementary to each other in that they comprise transistors having complementary carrier types, i.e., the transistors 31A and 31B are of p-carrier type and the transistors 32A and 32B are of n-carrier type. The gates of the transistors 31A and 32A are connected to the input node 302, and the gates of the transistors 31B and 32B are connected to the input node 304.
The transistor 33 supplies bias current to the differential pair 31A and 31B. The transistors 38A and 38B comprise a current mirror. The transistor 38A sinks bias currents from the transistors 31A and 36A, and the transistor 38B sinks bias current from the transistors 31B and 36B. The bias current supplied by the transistor 33 is equal in magnitude to the sum of the bias current sunk by the transistors 31A and 31B. When the voltage differential between the nodes 302 and 304 is zero, the transistors 38A and 38B sink equal bias currents.
Similarly, the transistors 37A and 37B comprise a current mirror. The transistor 37A supplies bias current to the transistors 32A and 35A, and the transistor 37B supplies bias current to the transistors 32B and 32B. The transistor 34 sinks bias current from the differential pair 2A and 2B. The bias current sunk by the transistor 34 is equal in magnitude to the sum of the bias current supplied by the transistors 32A and 32B. When the voltage differential between the nodes 302 and 304 is zero, the transistors 37A and 37B supply equal bias current.
The gate of the transistor 37A is connected to its drain, as well as to the gates of the transistors 33 and 37B. Because the gate of the transistor 37A is connected to its drain, it is biased in its saturation region as long as its gate-supply voltage VGS has a negative value higher than VTP, the pMOSFET threshold voltage. Consequently, the transistors 33 and 37B are also biased in their saturation regions within a margin of VTP. Similarly, the gate of the transistor 38A is connected to its drain, as well as to the gates of the transistors 34 and 38B. Because the gate of the transistor 38A is connected to its drain, it is biased in its saturation region as long as its gate-supply voltage VGS is more positive than VTN, the nMOSFET threshold voltage. Consequently, the transistors 34 and 38B are also biased in their saturation regions within a margin of VTN.
The transistors 32B and 35B are arranged as a folded-cascode pair. The transistor 35B is a pMOSFET, so that the folded-cascode pair 32B and 35B is comprised of transistors having complementary carrier types. The cascode transistor 35B provides impedance translation. That is, the impedance at the node 312 is significantly smaller than the impedance at node 306. Similarly, the transistors 31B and 36B are arranged as a folded-cascode pair with complementary carrier types, where the impedance at the node 314 is much smaller than the impedance at the node 306. The use of the cascode transistors 35B and 36B provides a high output impedance, which helps to provide a high amplifier gain because gain is determined by the product of the input transconductance and the output impedance.
The transistors 35A and 32A, and 36A and 31A, are arranged as folded-cascode pairs having complementary carrier types. The gate of the transistor 35A is connected to its drain, and the gate of the transistor 36A is connected to its drain, so that the transistors 35A and 36A are biased in their saturation regions. The gates and drains of the transistors 35A and 36A, which are at the same potential, are connected to the gates of the transistors 35B and 36B, and, thereby, bias them.
FIG. 4 is a circuit schematic diagram of a self-biased, high-gain differential amplifier disclosed in U.S. Pat. No. 4,937,476. The purpose of the comparator 40 is to convert VIN, which typically has TTL level signals, to a CMOS compatible VOUT, wherein the switching level is determined by the value of VREF. A CMOS transistor pair comprised of the p-type transistor 41 and the n-type transistor 42 are coupled in series between the nodes 471 and 472. The node 471 is coupled to a voltage supply, such as VCC, through a p-type transistor 44. The node 472 is coupled to VSS, which in this case is ground, through an n-type transistor 45. The drains of the transistors 41 and 42 are coupled together to the gates of the transistors 44 and 45. The gates of the transistors 41 and 42 are driven by the signal VREF.
Also coupled in series between the nodes 471 and 472 is another pair of CMOS transistors formed by p-type transistor 46 and n-type transistor 47. The gates of the transistors 46 and 47 are coupled together to receive VIN, and the drains of these two transistors 46 and 47 are coupled to drive the gates of a third set of CMOS transistors 48 and 49. A signal VCOMP is obtained at the drain junction of the transistors 46 and 47. VCOMP is coupled to drive the gates of a CMOS inverter formed by the transistors 48 and 49. The P-type transistor 48 and n-type transistor 49 are coupled in series between VCC and VSS, and VOUT is obtained from their drain junction.
The comparator 40 is actually a differential amplifier. In operation, the transistors 41 and 42 are identical in size and structure to the transistors 46 and 47, respectively. This is done so that both CMOS pairs have identical electrical behavior. The transistors 44 and 45 are utilized to provide bias for the transistors 41, 42, 46 and 47. Because the transistors 41 and 42 conduct together, the connection at their drains provides a biasing voltage VBIAS, which is then coupled to the gates of the transistors 44 and 45. This results in a self-biasing technique, wherein the transistors 41 and 42 operate in their active regions in spite of variations attributed to processing and temperature.
The size of the transistors 41, 42, 44 and 45 are chosen so that under typical conditions for processing, temperature and VCC, the transistors 41 and 42 are biased substantially in the center of their active region. Under certain conditions, the bias point of the transistors 41 and 42 will shift away from the center of the active region, either above or below the center, depending on the nature of the conditions. However, due to the negative feedback provided by the transistors 44 and 45 at nodes 471 and 472, and through the negative feedback inherent in the self-biasing technique, the shift in the bias point will be minimized, and the bias point will remain within the active region of the transistors 41 and 42.
Because the transistors 46 and 47 are identical in all respects to the transistors 41 and 42, when VIN is equal to VREF, the transistors 46 and 47 will become biased identically to the transistors 41 and 42. That is, the transistors 46 and 47 will also be biased in the active region. Therefore, the VCOMP voltage on the drain junction of the transistors 46 and 47 will be equal to the voltage VBIAS VBIAS, along with VCOMP, will have a value somewhere between the high state and the low state of VIN.
When VIN transitions from a low state to a high state, then VCOMP will switch from a high level to a low level, with the center of the switching region at or very near to the point where VIN equals VREF. Furthermore, the switching characteristic of VCOMP will be sharp about the point where VIN equals VREF, with VCOMP making a full transition from a high state to a low state for a small change in VIN. The transistors 48 and 49 serve as an inverter and amplify VCOMP further in order to obtain a full output swing from VCC to VSS as VOUT.
An n-type device 473 has its gate coupled to the node 471 and its drain and supply coupled to VSS. The device 473 is coupled to function as a capacitor. When VIN switches from a high state to a low state, VCOMP switches from a low state to a high state, and device 473 provides some of the charging current necessary to charge the parasitic capacitance on VCOMP, thereby speeding the rise time of the comparator. It should be noted that a p-type device 474 can be coupled to the node 472 to improve the fall time of the comparator.
FIG. 5 shows a differential amplifier circuit 50 disclosed in U.S. Pat. No. 4,958,133. The purpose of differential amplifier 50 is to amplify differential input voltages VA and VB of inputs A and B, respectively, whose common-mode component can vary over an extremely wide range of voltages. The extended range for the common-mode voltages is to the two rails, shown to be Vcc and Vss in FIG. 5, wherein the differential-mode gain of the amplifier still remains sufficiently high for the amplifier to be functional over this range of voltages.
The amplifier 50 is coupled to receive two differential inputs A and B, as voltages VA and VB, on lines 511 and 512, respectively, and to provide a single-ended output VOUT on a line 513. The amplifier 50 is completely complementary and is substantially symmetrical about nodes 520 and 521. The transistors 51a-52a and 55a-58a reside to the left of the nodes 520 and 521 in FIG. 5 and are applicable to the amplification of input signal A. The transistors 51b-52b and 55b-56b reside to the right of the nodes 520 and 521 in the drawing of FIG. 5 and are applicable in the amplification of input signal B. The transistors 53 and 54 are at the center of the symmetry and are applicable to both sides of the circuit.
The transistor 53 is a p-type device coupled between the node 520 and a supply voltage (positive rail voltage), which in this instance is Vcc. The transistor 54 is an n-type device coupled between the node 521 and a supply return Vss (negative rail voltage), which in this instance is ground. The gates of the transistors 53 and 54 are coupled together, and these two transistors 53 and 54 operate as a complementary pair. The transistors 55a-58a are coupled in series between Vcc and Vss. The transistor 55a is a p-type device having its supply coupled to Vcc and its drain coupled to the supply of the transistor 57a. The transistor 57a is also a p-type device having its drain coupled to the drain of the transistor 58a. The transistor 58a is an n-type device and has its supply coupled to the drain of the transistor 56a. The transistor 56a is also an n-type device and has its supply coupled to Vss. The gates of the transistors 55a-58a are coupled together on the line 522, wherein the line 522 is also coupled to the gates of the transistors 53 and 54.
The transistors 55a and 56a form the first complementary transistor pair in the series leg, while transistors 57a and 58a form the other complementary transistor pair of this series leg. Conversely transistors 55b-56b are also coupled in series between Vcc and Vss equivalently to the transistors 55a-58a. The transistors 55b and 56b operate as the first complementary transistor pair and the transistors 57b and 58b operate as the other complementary transistor pair in the right series leg. The gates of the transistors 55b-58b are coupled together to the line 522.
The transistor 51a is a p-type device having its supply coupled to the node 520 and its drain coupled to the drain-supply junction of the transistors 56a and 58a. The transistor 52a is an n-type device having its supply coupled to the node 521 and its drain coupled to the drain-supply junction of the transistors 55a and 57a. The gates of the transistors 51a and 52a are coupled together to the line 511 for accepting input A. The transistors 51a and 52a operate as a complementary pair.
The transistor 51b is a p-type device having its supply coupled to the node 520 and its drain coupled to the drain-supply junction of the transistors 56b and 58b. The transistor 52b is an n-type device having its supply coupled to the node 521 and its drain coupled to the drain-supply junction of the transistors 55b and 57b. The gates of the transistors 51b and 52b are coupled together to the line 512 for accepting input B. The transistors 51b and 52b operate as a complementary transistor pair.
It is to be noted that the amplifier 50 is completely complementary since each transistor device has a complementary counterpart of the opposite conduction type. Further, the amplifier 50 is symmetrical except for the “short-circuit” of the drains 57a and 58a to the line 522. This “short-circuit” is denoted as BIAS in FIG. 5, and the voltage at this point is referred to as VBIAS. At the right (B-input side) side of the circuit, drains of the transistors 57b and 58b are not coupled to the line 522. Instead these drains are coupled to the output line 513, wherein an output from the amplifier 50 is taken from the line 513 as VOUT.
It is to be further noted that all of the transistors of the amplifier 50, except for the transistors 53 and 54, are comprised of matched device pairs. The matched pairs are denoted by the same reference numeral and differentiated by the suffix a or b. For example, the transistors 51a and 51b comprise one of the matched pairs.
Each of the transistor pairs 51a and 58a, 51b and 58b, 52a and 57a, and 52b and 57b, comprises a “folded-cascode” pair. Each of these transistor pairs comprises a cascode pair since the drain of the first device in the pair is cascaded with the supply of the second device in the pair in typical cascode fashion. Each of these pairs is “folded” since the two devices in each pair are of opposite conduction type. Therefore, the small-signal current output from the drain of the first device in the pair “folds around” when it enters the supply of the second device in the pair.
The BIAS node 523 provides the bias voltage VBIAS for the amplifier 50. The bias is generated by the negative feedback from the drains of the transistors 57a and 58a to the gates of the transistors 55a-58a, 55b-58b, 53 and 54. This negative feedback causes the bias voltage to be stable and insensitive to variations in processing, supply voltage, temperature, and common-mode input voltage. Because the bias for the amplifier 50 is generated internally to the amplifier itself, the amplifier provides a self-bias (no external biasing scheme is used).
However, none of the previously described prior arts are suitable for a receiver with IO supply voltage higher than its core MOSFET operating voltage. When the IO supply voltage is much lower than its I/O thick oxide MOSFET operating voltage (for example, a 1.5V HSTL/JEDEC 8-6 receiver, designed by 3.3V IO MOSFET process whose core MOSFET is operated at only 1.2V), the amplifiers in the prior arts do not function unless an extra supply voltage, such as VDDIO of 3.3V or VCC disclosed in U.S. Pat. No. 4,958,133, is used to supply the operational amplifier. Other solutions without using an extra supply of a voltage higher than VDDIO may introduce a low Vt MOSFET which has the same gate oxide thickness as the thick gate oxide device as original IO devices. Since the threshold voltage is lower, the prior art can function under very low supply voltage. However, extra implant steps and masks are necessary during the manufacturing process of the receiver, which increases the cost.
Alternatively, the amplifier may amplify the received small signal successfully if all the MOSFETs in the prior arts are replaced with thin gate oxide devices. However, the thin gate oxide may be damaged since it cannot stand the input voltage higher than its operating voltage. For example, connecting a 1.2V thin gate oxide device to a 1.5V HSTL output may damage the gate oxide since 1.5V is higher than the 10-year life time voltage limitation of 1.2V.